CZ80CPU 8-bit microprocessor megafunction gener a l descript ion features implements a fast, fully-fu nctional , singl e -chip, 8 - bit microproc e ssor with th e sam e instru ction set as th e z80. programming features con t ain 208 bits of read/write m e mory th at ar e accessible to the programmer . the intern al r e gister s inclu d e an accumulator and six 8 - bit r e gister s that can be paired as three 16-bit registers. in additi on to general registers, a 16-bit stack-p o inter , 16-bit program-counter, and two 16-bit index register s are provided. the core has a 16-bit addr ess bus capable of directly accessing 64kb of memory sp ac e. it has 252 root in str u ction s with the reserv ed 4 bytes as prefixes, and accesses an additional 308 instructi o ns. ? ? ? ? ? ? control unit the microcod e-free design was d e veloped for reuse in asic and fpga implementati ons. it i s strictly synchr onou s, with n o internal tri- sta t e s and a sy nchr onou s re set . o 8-bit instructi o n decoder arithmetic-l ogic unit o 8-bit arithmetic and logical operati o ns symbol o 16-bit arithm etic oper ation s o boole a n mani pulation s register file unit o duplicate set of both general purpose and flag register s o two 16 -bit in dex registers interrupt con t roller o three m o des of ma skable i n terrupts o non mask abl e interrupt external mem o ry interfac e o can address up to 64 kb of program memory o can address up to 64 kb of data memory o can address up to 64 kb of input/output devices on-core dyn a mic memory r e fresh counter cast, inc . apri l 2004 page 1
cz8 0 c pu m e g a func tio n da ta she e t applications suitable for many embed d ed controller application s , includ ing industrial c o ntrol systems, poin t-of -sale term inals, and automotive contr o ls. block diagram addr_unit reset_control instruction_reg sp_reg pc_reg i_reg r_reg w_reg z_reg a addr_reg iff_reg im_reg bus_control alu nmi_control register_bank iy_reg ix_reg b_reg c_reg b'_reg c'_reg d_reg e_reg d'_reg e'_reg h'_reg l'_reg h_reg l_reg a_reg a'_reg f_reg f'_reg nmin reset clk waitn m1 mreqn iorqn rdn wrn rfshn haltn busak intn busrqn dotri atri control_tri cycle_control control_bus di di data bus data_reg do instruction; cycle bus cast, in c. page 2
cz8 0 c pu m e g a func tio n da ta she e t pin description name type polarity / bus size descrip t ion c l k i r i s e clock feeds internal clo c k co unters and all synchro n o u s c i rcuits. r e s e t i h i g h hardware reset input a high o n this pin fo r two clo c k cycles while the o s cillato r is running resets the devi ce. w a i t _ n i l o w wait a low on this pin indicates to the cpu that the addres sed memory or i/o devices are not ready for a dat a transfer. t h e cpu continues to enter a wait state as long a s this signal is active. i n t _ n i lo w i n terrupt re quest this signal is generate d by an i/o device. the cpu honors a reque s t at the end of the curr ent instruction, if the internal software-c ontrolle d interrupt enable flip-flop is enabled. n m i _ n i lo w non-mask a bl e interrup t this pin has a hi gher priority then int_n a n d is always recognized at the end of the current instruction independent of the status of the interrupt enable flip-flop and forced the cpu to restart at address 0066h. b u s r e q _ n i l o w bus request it has higher p r io rity than nmi_n and is always recognized at the end of t h e current machine cycles. active state on this pi n forces the cpu address bus , data bus, and control signal to go to a high-i mpedance stat e, so that other devices can c o ntrol these lin e s. busak_ n o lo w bus request acknowledgment low on this pin indicates to the reque s ting device that the cpu address b u s, data bus, a n d control signal have e n tere d their high-impedance state and it can no w co ntrol these lines. m 1 o h i g h machine cycl es one this p i n together with mreq_n indic a tes that the c u rrent machine cycle is the opcode fetch cycle of an instruction execution. it togeth er with iorq_n i n dicates an int e rrupt acknowledge cycle. addr_o addr_tri o o 8 high address bus addr_o forms a 16-bit address bus. the addr ess bus provid es the address for memory data b u s exchanges ( u p to 64k byte s) and for i/o device exchang e s. data_i data_o data_tri i o o 8 8 high data bus (input/output, 3-s t ate) 8- bit bidir e ctional data bus, used for da ta exchanges with memory and i/ o. mreq_n mreq_tri o o lo w high memory request indicates that the addre ss bus holds a valid address f o r memory read or memory write operation. ioreq_n ioreq_tri o o lo w high i/o req u est indicates that the lower half of the a ddress bus holds a v a lid i/o address for an i/o read or write operation. rd_n rd_tri o o lo w high read rd_n indicates that the cpu wants to read data fro m memory, or that an i/o dev i ce or memory should use this signal to gate data onto the cpu data bus. wr_n wr_tri o o lo w high write indicates that the cpu data bus hol d s valid data to be stored at the addressed memory or i/o device. r f s h _ n o l o w refresh timing this signal together with mreq_n, in dicates that the lower seven bits of the system?s addre ss bus can be used as a refre s h address to t h e system?s d y namic memories. h a l t _ n o lo w halt state low on this pin indicates that the cpu has executed a halt instruction and is awaiting either a no nma s kable o r a ma skable interrup t befo re o p eratio n can resume . functional description the CZ80CPU core is p a rtiti o ned into m o dules as shown in the block diagram and described below. cycle con t rol the main c o n t rol machin e, which synchr onizes all the ot her s . it h a s an instruc t ion register an d all register s controlled interrupts, bus r e quest cy cl e, wait sta t es et c. thi s unit c o ntrol s bus c o ntrol signal s too . bus cont ro l registers are triggered on the falling edge and or gate s. these ar e used to form the bus c o ntr o l timing, changed on b o th clock edges. thi s is th e only unit that has r e gister s synchr onized on the fallin g clock edge. cast, in c. page 3
cz8 0 c pu m e g a func tio n da ta she e t add r ess u n it this uni t controls all operations on addre s s e s (c alcula t e s the n e xt in structi o n addr es s, ne sted d a ta addres s , jump and return address etc.) and increments and decr ement s the 16-bit addr re gister. it inclu d es pc_reg (program cou n ter), sp_reg (stack pointer), i_reg (i nter rupt register) and r_reg (refresh regi ster). nmi cont rol this uni t detects a f a lling edge on the n m in pin. if detect ed , the in ternal nmi register is set and this cau s es a non-m a sk abl e interrupt service cycle. reset cont rol this uni t controls th e state of external si gnal resetn. i f it has v a lue ?0? for at least three full clock cycles, then it set s the int e r n al synchr on ous re set sig n al (rst ) to ?1 . ? registe r bank this includes all the comm only used reg i ster s (based an d altern ativ e) and the l o gic element n eeded to ch ange the dat a in th ese regi ster s. arit hmetic -logic unit (alu) the unit accumulator and flag register s, and perform s 8-bi t arithmetic and logic operati o ns, 1 6 -bit arithmetic operati o ns (w ithout increm ent and decre m ent), bit op eration s , and set s the fl ag register . verifi ca tion met h ods the CZ80CPU core?s func tionality was verified by means of a prop rietary hardware model e r. the same sti m ulus was applied to a hard ware model that c o ntain e d the original zilog z84c00 chip, and the results comp ared with the core? s sim u lation outpu t s. device utilization & performance the CZ80CPU is designed to run at frequ e ncies up to 80 mhz on a typical 0.5 - micron process and it uses less than 8k gates depending on the technol o gy. the cz8 0 cp u is a technology independent desi gn that can be implemented in a variety of process tech nologies. supported device utilization performanc e family tested les memory memory bit s f max cyclone e p 1 c 6 - 6 3 8 9 7 - - 8 2 m h z stratix e p 1 s 1 0 - 5 3 6 2 1 - - 9 9 m h z stratix-ii e p 2 s 1 5 - 3 3 0 4 8 - - 1 3 8 m h z note: results op ti mized for speed cast, in c. page 4
cz8 0 c pu m e g a func tio n da ta she e t cast, in c. page 5 deliverables ? ? ? ? ? ? ? ? vhdl or veril o g hdl sourc e code post-synthesi s edif netli s t (netlist lic ense) testbench (self-checking) vect ors f o r te sting the c o re place & rout e scripts (n etli st licen se) simulation sc ript synthesi s script documentation verifi ca tion met h ods the CZ80CPU core?s func tionality was verified by means of a prop rietary hardware model e r. the same sti m ulus was applied to a hard ware model that c o ntain e d the original zilog z84c00 chip, and the results comp ared with the core? s sim u lation outpu t s. cont act infor m a t ion cast, inc. 11 stonewall court woodcliff lak e , new jersey 07677 usa phone: +1 201-391-8 300 fax: +1 201-391-8 694 e-mail: info@c ast-inc . com url: www.cast-in c .com this m e gafunction devel o ped by the processor experts at evatr o nix sa cop y rig h t ? 2 0 0 4 , ca st , i n c. a l l r i g h ts r e s e rved . conte n t s sub j ec t to c h ang e w i th out n o t i c e .
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